1. Field of the Invention
The present invention relates to an IC package, and more particularly, it relates to an IC package having electric conductor lines which transmit high speed signals from an exterior device to an interior integrated circuit.
2. Description of the Related Art
A semiconductor chip having an integrated circuit capable of treating high speed signals, such as signals of several giga bits per second (Gb/s), is hermetically encapsulated in a package body. FIG. 13 to 15 of the attached drawings show a typical conventional IC package 71.
The IC package 71 comprises a semiconductor chip 72 and a dielectric package body for encapsulating the semiconductor chip 72. The package body comprises a bottom member 73 for supporting the semiconductor chip 72 at the central region of the bottom member 73, dielectric annular members 74a and 74b surrounding the chip supporting region, and a cap member 75 covering the dielectric annular members 74a and 74b and the chip supporting region. Electric conductor lines 76 formed on the surface of the dielectric annular member 74a are obtained by patterning a conductor film, for transmitting high speed signals between an exterior device and the interior integrated circuit and for supplying power to the interior integrated circuit. The semiconductor chip 72 is provided with electrode pads which are connected to the respective one ends of the electric conductor lines 76 by bonding wires 79; the respective other ends of the electric conductor lines 76 being connected to outer leads 77.
The electric conductor lines 76 for a transmission of signals and a supply of power are formed between the dielectric annular members 74a and 74b, i.e., on the surface of the dielectric annular member 74a, and further, the conductor lines 76 are arranged between a conductor film 78a to be grounded and formed on the lower surface of the dielectric annular member 74a and a conductor film 78b to be grounded and formed on the upper surface of the dielectric annular member 74b, to thus provide transmission lines having a predetermined characteristic impedance.
In the above-described arrangement, it is necessary to expose the end portions of the conductor lines 76 at the upper dielectric annular member 74b, to allow these end portions to be connected to the leads 77 and the bonding wires 79, and accordingly, the width of the lower dielectric annular member 74a is made larger than the width of the lower dielectric annular member 74b located intermediately on the lower dielectric annular member 74a. The central portion of the upper surface of the lower dielectric annular member 74a, indicated by the character X in FIG. 15, is covered by the upper dielectric annular member 74b; the inner and the outer portions, indicated by the character Y, are exposed to the air.
Accordingly, the waveguide of the conductor lines 76 is constituted by a strip line at the central portion X, and a microstrip line at the inner and outer portions Y, resulting in a problem that the magnitude of the characteristic impedance is not uniform and a reflection loss occurs due to an impedance mismatching.
Further, one of the conductor lines 76 is a power supply line through which a direct current is supplied, however, the level of the current changes depending on the operation of the components in the integrated circuit and current through the power supply conductor line 76 includes components of an alternating current, and thus the voltage of the current passing through the power supply conductor line 76 is affected by the characteristic impedance. The variation of the power voltage varies largely due to the characteristic impedance which becomes larger at the microstrip line, and a problem arises in that the operation of the integrated circuit is unstable.
To solve these problems, Japanese Unexamined Patent Publication (Kokai) No. 61-239650 discloses an IC package in which portions of the conductor lines in correspondence with the area of the microstrip line are broadened to effect an impedance matching. This arrangement, however, causes a lowering of the degree of integration and an increase in the length of the dielectric annular members 74a and 74b, which is increased with the number of the conductor lines 76, it becomes difficult to design an IC package having a small size.